As a technology that the present inventors examined, the following technology is conceivable in a semiconductor device, for example, a SiP (System in Package) and the like.
In connection with minuteness of semiconductor manufacturing technologies, insufficiency of I/O performance of the semiconductor chip is becoming aggravated. This is because of the following circumstances. Since the improved minuteness allows the circuit mounted in a semiconductor chip to increase in number, the quantity of I/O processing (the number of I/O's, their speed, etc.) necessary for the semiconductor chip to realize functions increases. On the other hand, since the number of terminals of the semiconductor chip is limited by wire bonding etc. and is governed by a chip size, i.e., it does not increase by the minuteness, I/O processing performance is not improved.
In these circumstances, in order to solve the insufficiency of I/O performance of the semiconductor chip, there is actively developed a three-dimensional (3D) coupling technology in which terminals are disposed on the top face and down face of the semiconductor chip two-dimensionally and a plurality of semiconductor chips are stacked, whereby information is transferred among the stacked chips.
For this reason, in the case where the SiP is formed by stacking the semiconductor chips on which the 3D coupling technology is mounted, 3D coupling and a conventionally existing interconnect network inside the semiconductor chip need to be coupled.
For example, as one example of the technology of performing data communication among the chips by the 3D coupling technology of an inductive coupling method, there can be enumerated a technology described in JP-A-2006-066454.
Moreover, as one example of the technology of performing data communication among the chips by the 3D coupling technology of a capacitive coupling method, there can be enumerated a technology described in JP-A-2004-253816.